A typical image sensor senses light by converting impinging photons into electrons and collecting (integrating) them in sensor pixels. After the integration cycle is completed charge is converted into a voltage that is supplied to the output terminals of the sensor. An example of pixel circuit diagram (101) for an advanced active pixel CMOS image sensor array (100) is shown in FIG. 1. In this example, the charge to voltage conversion is accomplished by integrating charge in a special potential well 102 of a p-channel transistor 103 (U.S. patent provisional application 60/245,942 to Hynecek). Integrated charge causes change in the threshold voltage of transistor 103. Turning on the row addressing transistors 104, and supplying a small bias current to the pixels from the drain bias terminal 110 through the column current sources 116, senses the pixel outputs and drives the column sense lines 105. After the pixel signal is transferred to the horizontal scanner-buffer 112, and is scanned out, transistors 107 reset the pixels in selected rows. The pixel reset can alternately be performed immediately after the signal transfer into the buffer if the buffer is provided with a row data storage capability. The pixel reset is accomplished by applying pulse 117 to the reset transistor gate buss 109. The reset causes charge collected in the potential wells 102 to flow out into the drains 111. In the next step a clocking pulse is applied to the clocking terminal 115 of the vertical scanner 113, and the next row 106 of the array 100 is processed. The vertical scanner is initiated by a pulse applied to terminal 118. The sequence is repeated until the whole array is scanned. Horizontal column scanning is accomplished by applying clocking pulses to the horizontal scanner clocking input 114 and the register is initiated by pulse applied to the terminal 119. The pixel signal is delivered to the sensor output terminals 116 via the buffer amplifier 108.
Another example of the pixel suitable for use in this invention is described in the U.S. Pat. No. 6,091,280 to Hynecek. It is clear to those skilled in the art that any pixel that is reset through the column lines rather then through the row lines can be used in this invention. For the sake of brevity the description of many such pixels will not be given here.
The above-described array scanning method is known in the art as the “rolling shutter scan”. Each line has the same charge integration period length, but the integration does not start and stop simultaneously for all the rows of the array as in the “snap shot mode”.
Both the snap shot and the rolling shutter scanning modes have a disadvantage in limiting the sensor DR. For brightly illuminated pixels, it is necessary to have a short integration time, while for dimly illuminated pixels, it is desirable to extend the integration period as long as possible to integrate more charge. However, when all the pixels of the same row, or the whole array, are reset simultaneously, they all have the same integration time. The sensor DR is then given by the ratio of the maximum pixel well capacity to the pixel noise floor.
By modifying the standard architecture of the typical CMOS image sensor array, and providing selective pixel reset to each pixel individually in each row or in the whole array, depending on the amount of integrated charge, eliminates this common drawback. The present invention thus provides a significant DR advantage in comparison to the standard CMOS image senor architectures as well as to all standard CCD image sensor architectures where the pixels in one row are always reset at the same time.